Method for testing for the presence of faults in digital circuits

ABSTRACT

A method of testing for the presence of faults in digital logic circuits is described. The method involves re-ordering a number of test vectors for testing digital circuits by selecting faults at random from an original fault list to form a sample fault list F N  and then forming a vector set T N−1  and then simulating the vector set T N−1  against the fault list F N . Any vector from the set T N−1  which does not detect any fault is discarded and the remaining vectors are saved as vector set T N . The method steps are repeated N times (with N having a value of 1 to M. Duplicated vector patterns in each vector set are removed and then the final vector set is initialized to produce a final vector set T t .  
     Embodiments of the invention are described.

[0001] The present invention relates to a method of testing for thepresence of faults in digital logic circuits. In particular, theinvention also relates to a method for re-ordering “test vectors” toachieve an improved ordering which maximises the fault coverage on adigital circuit which is reached with a limited number of test vectors.

[0002] The testing of faults in digital circuits using test vectors iswell known. This is typically done by applying a test vector, which is aset of binary values, to a digital circuit on either the primary inputsof the circuits or via a “scan chain” connecting the state elements,which are normally flip-flops, within the digital circuit and expectedresponse values on the circuit primary inputs are captured within thestate elements, prior to being accessed via the scan chain. The term“fault coverage” is defined as a measure of the number of faults withinthe circuit which an individual test vector or set of test vectors willdetect. The common fault model is “stuck-at” faults which arerepresented by short-circuits to power or ground on the primary inputsor outputs of logic gates within the circuit. Fault coverage is measuredusing a fault simulator which determines whether the output response ofthe circuit is affected.

[0003] A large number of existing methods for generating test vectors isknown and are published in the public domain. The best known is the RothD Algorithm, originally published in 1966 and J. P. Roth “Diagnosis ofAutomota Failures: A Calculus and a Method”, IEM Journal of Research anDevelopment, Vol 10, No. 4, pp. 278-291, July, 1966.

[0004]FIG. 1 depicts an example of a test vector which is a list ofbinary values to be applied to the digital circuit under test via theprimary input or via a scan chain. A scan chain is a method of seriallyloading values into the flip-flops in the digital circuit. This is awell known and widely published design technique. In the prior artexample shown, two scan chains are depicted, although any number of scanchains may be used.

[0005] Existing methods of testing for faults on an integrated digitalcircuit suffer from the principal disadvantage that a very large amountof test vectors is required in order to provide a satisfactory faultcoverage. This can take a relatively long time and requires a relativelylarge amount of memory and is a limiting factor in the design andtesting of such circuits.

[0006] An object of the present invention is to obviate or mitigate atleast one of the above-mentioned disadvantages.

[0007] This is achieved in the broadest sense by using randomly selectedfault lists to select subsets of test vectors.

[0008] According to one aspect of the present invention, there isprovided a method of maximising the fault covering on an integrateddigital circuit by re-ordering a number of test vectors for testing thedigital circuit, said method comprising:

[0009] a) providing an initial set of test vectors T₀;

[0010] b) providing an original set of faults F₀;

[0011] c) selecting faults at random from the original fault list toform a sample fault list F_(N);

[0012] d) forming a vector set T_(N−1) and simulating the vector setT_(N−1) against fault list F_(N);

[0013] e) discarding any vector from the vector set T_(N−1) which doesnot detect any faults, and

[0014] f) saving the remaining vectors as vector set T_(N), repeatingthe above steps a) to e) N times with N having a value of 1 to M so thatthe end of N steps saving test vectors T₀ to T_(M);

[0015] g) removing duplicate vector patterns in each vector set T_(N);and

[0016] h) initialising the final vector set and appending vector setsV_(M) to V₀ to produce a final vector set T_(F).

[0017] Preferably, in steps a) to f) M is 10 and these steps aretherefore repeated ten times.

[0018] Preferably, the method of removing duplicate vector patterns isachieved by:

[0019] i) copying the original fault list F₀ to provide a secondaryfault list G₀;

[0020] j) fault simulating vector set T_(N) against G_(N) and deletingany vector s which find no faults;

[0021] k) saving the resulting vectors as vector set V_(N) and savingthe list of undetected faults as list G_(N−1);

[0022] l) repeating step g) to i) M+1 times with N having values M to 0;

[0023] These and other aspects of the invention will become apparentfrom the following description, when taken in combination with theaccompanying drawings, in which:

[0024]FIG. 1 is a depiction of a test vector;

[0025]FIG. 2 is a flow chart of the steps involved in the method ofre-ordering test vectors for maximising the fault coverage on a digitalcircuit;

[0026]FIG. 3 is a legend to terms used in the flow chart of FIG. 1, and

[0027]FIG. 4 is an example of a graph of fault coverage showing thenumber of faults detected against the number of vectors for the originalvectors and vectors after using the new method/algorithm.

[0028] Reference is first made to FIGS. 2 and 3 of the drawings whichdepict a flow chart of a sequence of steps involved in re-ordering testvectors to provide a test vector generation pattern for maximising thefault coverage on an integrated digital circuit using a limited numberof test vectors.

[0029] In stage 1, (steps a) to f) an initial set of vectors areprovided (step a) and these are copied to form a set of test vectors T₀to place these vectors in a near-optimal order for detecting a set offaults F₀. Stage 1 has two principal steps. In the first step (step 10),a list of faults is selected at random with a probability of 2^(−N) fromthe original fault list F₀ to form a sample or subset fault list F_(N).The second major step (step 12) in stage 1 is fault simulating thevector set T_(N−1) repeatedly against the fault list F_(N) and thendiscarding any vector which does not detect any faults. In step 12, theordering of individual vectors within the vector set are alternatelyreversed and randomised. The resulting vector set, that is those that doresult in the finding of faults, is saved as vector set T_(N).

[0030] The two major steps 10 and 12 are repeated N times with N takingthe value 1 to M where M is 10 in this example.

[0031] At the completion of step 12, there are ten sets of vectorssaved, T₁ to T₁₀.

[0032] At the end of the stage 1, the method involves stage 2 whereinduplicate vector patterns are removed from the vector pattern listT_(N). In this case the original fault list F₀ is again copied anddenoted as fault list G_(M) (step 14). In the next step in stage 2, step16, the vector set T_(N) is fault simulated against the fault list G_(N)and any vectors which result in no faults being found are deleted. Afterthe fault simulation, the resulting vector set is saved as V_(N) and thelist of undetected faults is saved as G_(N+1). Stage 2 is repeated Mplus 1 times, with M taking values M down to zero where M is 10.

[0033] The final stage in the methodology is stage 3 in which the finalvector set is initialised (step 18) and vector sets V_(M) to V₀ areappended together to produce a final vector set T_(F) (step 20).

[0034] The re-ordering of the generated test vectors in the waydescribed above allows a digital integrated circuit to be tested muchquicker than with the prior art test vector ordering, such that adigital circuit can be tested in typically one tenth of the time usingthe prior art re-ordering test vector set. This means that much lessmemory is required and the design process is speeded up, resulting in aconsiderably economic benefit.

[0035]FIG. 4 depicts a graph of faults detected against a number ofvectors. It will be seen that a large number of faults are detected forvectors re-ordered after the new re-ordering method compared to anoriginal number of vectors where there is less than about 700 vectorsused. This increase is most dramatic for a lower number of vectors, suchthat this re-ordering algorithm maximises the fault coverage for a lowernumber of vectors when testing an integrated digital circuit.

[0036] Various modifications may be made to the re-ordering methodologyhereinbefore described, without departing from the scope of theinvention. For example, the repetition of each stage may take values inexcess of or less than 10, although this will have an effect on the timetaken to test the digital circuit. In addition, the probability factorof (X^(−N)) 2^(−M) in this example may be varied. Increasing the valueof X from 2 will reduce the time taken for the re-ordering but willreduce the quality of result and decreasing the value X from 2 willresult in a longer time for re-ordering but will be more accurate. Inaddition, the duplicate vector patterns in the vector sets are removableby an alternative method wherein a text search is conducted through thelist of files of vector patterns to look for identical vector patternsand once the identical vector patterns have been identified they aredeleted. It will be appreciated that after re-ordering the vectors, alarge number of faults are detected by any size of subset of theoriginal vectors than by the original vectors themselves and, asindicated above, this significantly reduces the test time for thedigital circuit and requires less memory capacity in the test apparatus,resulting in a more effective and more efficient test system.

1. A method of maximising the fault coverage on an integrated digitalcircuit by re-ordering a number of test vectors for testing the digitalcircuit, said method comprising: a) providing an initial set of testvectors T₀; b) providing an original set of faults F₀; c) selectingfaults at random from the original fault list to form a sample faultlist F_(N); d) forming a vector set T_(N−1) and simulating the vectorset T_(N−1) against fault list F_(N); e) discarding any vector from thevector set T_(N−1) which does not detect any faults, and f) saving theremaining vectors as vector set T_(N), repeating the above steps a) toe) N times with N having a value of 1 to M so that the end of N stepssaving test vectors T₀ to T_(M); g) removing duplicate vector patternsin each vector set T_(N), and h) initialising the final vector set andappending vector sets V_(M) to V₀ to produce a final vector set T_(F).2. A method as claimed in claim 1 wherein in steps a) to f) M is 10 andthese steps are therefore repeated ten times.
 3. A method as claimed inclaim 1 wherein the list of faults selected from the original list offaults have a probability of X^(−N) to produce subset fault list F_(N).4. A method as claimed in claim 2 wherein the list of faults selectedfrom the original list of faults have a probability of X^(−N) to producesubset fault list F_(N).
 5. A method as claimed in claim 3 wherein X=2.6. A method as claimed in claim 1 wherein the step of removing duplicatevector patterns is achieved by: i) copying the original fault list F₀ toprovide a secondary fault list G₀; j) fault simulating vector set T_(N)against G_(N) and deleting any vectors which find no faults; k) savingthe resulting vectors as vector set V_(N) and saving the list ofundetected faults as list G_(N−1); l) repeating step g) to i) M+1 timeswith N having values M to 0;
 7. A method as claimed in claim 1 whereinthe step of removing duplicate vector patterns is achieved by conductinga text search through the list of files of vector patterns looking foridentical patterns, identifying the identical patterns and deleting theidentical patterns identified.